The present invention relates generally to integrated circuit packaging, and, more particularly, to integrated circuits having solder balls, also known as solder bumps, used to connect the integrated circuits electrically to external electronic components.
FIG. 1A is a cross-sectional side view of a portion of a conventional integrated circuit (IC) 100, and FIG. 1B is a magnified view of a section 150 of the IC 100. FIG. 1A shows the top metal layer 106 (e.g., M5) of the IC 100 with vias 104 extending downwardly (i.e., perpendicularly to the metal layers) to the next lower metal layer 102 (e.g., M4). Although not represented in FIG. 1A, the IC 100 has other metal and non-metal layers below the metal layer 102. On top of the top metal layer 106 is a passivation (PSV) layer 108 having a number of openings 110 down to the top metal layer 106. On top of the PSV layer 108 and coating the side walls of the openings 110 is a first polyimide (PI1) dielectric layer 112. On top of the PI1 layer 112 and filling the remainder of each opening 110 down to the top metal layer 106 is a metal (e.g., copper) redistribution layer (RDL) 114. The portions of the RDL layer 114 that fill the openings 110 are via structures (a.k.a. vias) 116 that electrically connect the RDL layer 114 to the top metal layer 106.
As indicated in FIG. 1B, in order to accommodate a 7-micron thick PI1 layer 112, the bottom of each opening 110 in the PSV layer 108 is 40 microns wide in order to provide a metal via 116 having a bottom width of 26 microns.
On top of the RDL layer 114 is a second polyimide (PI2) dielectric layer 118 having a single, large opening 120. Filling the opening 120 in the PI2 layer 118 and extending beyond the opening 120 over a portion of the PI2 layer is under-ball metallization (UBM) 122. Lastly, on top of the UBM 122 is a solder ball 124.
One of the goals of the design of the IC 100 is to electrically connect the solder ball 124 and the top metal layer 106 with relatively low resistance (R-on) when the IC 100 is powered on. However, cracking can occur within the RDL layer 114 near the interface 160 between the solder ball 224 and the nearest via 116 due to stress and warpage of the RDL layer 114 resulting from repeated thermal expansion and contraction. Accordingly, it would be advantageous to have a low R-on bond pad design that is less susceptible to cracking due to stress and warpage.